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Per Pin Parametric Measurement Unit/Source Measure Unit AD5520
FEATURES Force/Measure Functions Force Voltage/Current, Measure Current/Voltage Force Current/Voltage, Measure Current/Voltage Force/Measure Voltage Range 11 V 4 Programmable Force/Measure Current Ranges 4 A, 40 A, 400 A, 4 mA Extended Current Ranges 40 mA and 160 mA with External Driver Clamp Circuitry and Window Comparators On Board Guard Amplifier 64-Lead LQFP Package APPLICATIONS Automatic Test Equipment Per Pin PMU, Shared Pin PMU, Device Power Supply Instrumentation Source Measure, Parametric Measurement, Precision Measurement GENERAL DESCRIPTION
The AD5520 is a single channel per pin parametric measurement unit (PPMU) for use in semiconductor automatic test equipment. The part is also suited for use as a source measurement unit for instrumentation applications. It contains programmable modes to force a pin voltage and measure the corresponding current or force a current and measure the voltage. The AD5520 can force/measure over a 11 V range or currents up to 4 mA with its on-board force amplifier. An external amplifier is required for wider current ranges. The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. The AD5520 is available in a 64-lead LQFP package.
FUNCTIONAL BLOCK DIAGRAM
COMPOUT0 COMPOUT1 COMPOUT2 COMPIN0 COMPIN1 COMPIN2
AVEE AVCC
AD5520
FOH FOH3 FOH2 FOH1 FOH0 MEASI5H
BW SELECT
FIN
CLAMP DETECT CLH CLL REFGND MEASIOUT G = 16 ISENSE INST AMP VSENSE INST AMP G=1
MEASI4H MEASI3H MEASI2H MEASI1H MEASI0H
MEASIL GUARDIN G=1 GUARD MEASVH MEASVL AGND
CLHDETECT CLLDETECT
MEASOUT
MEASVOUT COMPARATOR CPH CPOH CPOH CPL
STB
LOGICS
STANDBY
QM5 QM4
AC0 AC1 DGND CS DVDD
CPSEL
MSEL
FSEL
AM2
AM1
CPCK
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AM0
MOE
5%, AV = -15 = 10%, DGND 0 V. 70 noted.) AD5520-SPECIFICATIONS (AV ==+15 VAll specifications 0 VC to 5%,C,DVunless5 Votherwise AGND = 0 V, REFGND = 0 V,
CC EE DD
Parameter VOLTAGE FORCE MODE Force Control Output Voltage Range FOH Output Impedance FOH0 FOH1 FOH2 FOH3 Input Offset Error Gain Error Clamp Voltage Error2 CURRENT MEASURE/FORCE FOH0 FOH1 FOH2 FOH3 CURRENT MEASURE MODE High Sense Input Range, VMEASIxH Linearity3 Input Bias Current Input Bias Current Drift1 Output Offset Error
Min 11
Typ1
Max
Unit V k k mV % % FS A A A mA
Test Conditions/Comments RLOAD = 10 k, CLOAD = 50 pF
70 2.5 3 500 60 1 1
5 1
of FIN Set with external sense resistors MODE0, RS = 125 k MODE1, RS = 12.5 k MODE2, RS = 12.5 k MODE3, RS = 125
4 40 400 4 11 0.01 3 100 100 100 100 0.35
1 50
Gain Error Gain Error Temperature Coefficient4 MEASIOUT Output Load Current CMRR CURRENT FORCE MODE Input Offset Error Gain Error Clamp Current Error2 VOLTAGE MEASURE MODE Differential Input Range Low Sense Input Voltage Range Linearity3 Input Offset Error Input Offset Error Temperature Coefficient1 Gain Error Gain Error Temperature Coefficient4 Input Bias Current Input Bias Current Drift4 MEASVOUT Output Load Current CMRR4 AMPLIFIER SETTLING TIME4, 5 VSENSE Amp ISENSE Amp LOOP SETTLING4, 5 COMPIN2 = 100 pF 11 100
0.1 30 4 95
V % FSR nA pA/C mV mV mV mV % V/C mA dB mV % % FS V mV % FSR mV mV/C % mV/C nA pA/C mA dB s s
+11 V > VFOL > -11 V MODE0 MODE1 MODE2 MODE3 Gain of 16
@ DC With MODE0, MODE1, MODE2, MODE3 of FIN
10 1 1
5 15 0.03 2 1 50 4 73 20 12 450 285 170 2 1.8 5.75
+0.005 10
MEASVL +11 V > VMEASVH to VMEASVL > -11 V FIN = 0 V, Measured @ MEASVOUT
0.15 3
Gain of 1
@ DC To 0.2% To 0.2% Settling to within 0.024% of 8 V step MODE0 MODE1 MODE2, MODE3 MODE0 MODE1, MODE2, MODE3 MODE0, MODE1, MODE2, MODE3
COMPIN1 = 1000 pF COMPIN0 = 3000 pF
600 390 240 2.5 2.4 8.7
s s s ms ms ms
-2-
REV. A
AD5520
Parameter SLEW RATE
4, 5
Min
Typ1 Max 50 4.3 1.28
Unit mV/s mV/s mV/s V mV V mV mA s V M V M V M pF k pF
Test Conditions/Comments COMPIN2 = 100 pF COMPIN1 = 1000 pF COMPIN0 = 3000 pF VCPH > VCPL
COMPARATOR CPH, CPL Input Range Input Offset GUARD DRIVER Output Voltage Output Impedance Output Offset Voltage Load Current4 Output Settling Time4 ANALOG REFERENCE INPUTS Force Control Input Range Force Control Input Impedance Clamp Control Input Range Clamp Control Input Impedance Comparator Threshold Input Range Comparator Threshold Input Impedance Input Capacitance4 ANALOG MEASUREMENT OUTPUTS Voltage Measure Output Impedance Current Measure Output Impedance Multiplexed Sense Output Impedance Input Capacitance MEASIxH, MEASVH, FOHx LOGIC INPUTS Input Current Input Low Voltage, VINL Input High Voltage, VIHL Input Capacitance4 LOGIC OUTPUTS Output Low Voltage, VOL4 Output High Voltage, VOH4 POWER REQUIREMENTS AVCC AVEE Power Supply Rejection Ratio, PSRR1 FOH
11 7 11 130 400 4 0.5 11 1 11 1 11 1 3 2 3 1 8 1 0.8 2.0 3 0.4 2.4 +14.25 -14.25 +15 -15 -25 -16 -15 -55 -10 90 5 12 12 0.5 +15.75 +15.75
Capacitive Load Only
2
100 pF Capacitive Load
VCLH > VCLL
A V V pF V V V V dB dB dB dB dB dB V mA mA mA
All digital inputs together
ISINK = 2 mA ISOURCE = 2 mA For specific performance6
MEASOUT DC PSR DVDD IAVCC IAVEE IDVDD
100 kHz 500 kHz 1 MHz 100 kHz 500 kHz
Digital inputs at supply rails
NOTES 1 Typical values are at 25C and nominal supply, unless otherwise noted. 2 Full-scale = 11 V. 3 Full-scale range = 22 V. 4 Guaranteed by design and characterization but not subject to production test. 5 Force control amplifier dominates slew rate and settling time. 6 Operational with 12 V supplies, force/measure range is reduced to 8.5 V. Specifications subject to change without notice.
REV. A
-3-
AD5520 TIMING CHARACTERISTICS1, 2
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 5V 0 30 40 0 550 320 450 150 100 240 150 100 320 DVDD 10% 0 200 70 40 560 320 500 800 440 240 500 440 320
(AVCC = +15 V 5%, AVEE = -15 V 5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All specifications 0 C to 70 C, unless otherwise noted.)
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min s min ns min ns min ns min Conditions/Comments CS Falling Edge to STB Falling Edge Setup Time STB Pulse Width STB Rising Edge to CS Rising Edge Setup Time Data Setup Time CS Falling Edge to CPCK Rising Edge Setup Time CPCK Pulse Width CPCK to STB Falling Edge Setup Time STB Rising Edge to QMx, CLxDETECT Valid STB Rising Edge to CPOH, CPOL Valid Comparator Setup Time, MODE2, MODE3 settling Comparator Hold Time Comparator Output Delay Time Comparator Strobe Pulse Width
3.3 V
NOTES 1 See Figure 1. 2 All input signals are specified with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. Specifications subject to change without notice.
CS
t1
STB
t2
t3
t4
AMx, ACx, FSEL, MSEL, CPSEL
t5
CPCK
t6
t7
t8
QM4, QM5, CLHDETECT, CLLDETECT
t9
CPOL, CPOH
Figure 1. Timing Diagram
MEASVOUT OR MEASIOUT CPCK
t 11
CPOH, CPOL
t 10 t 12
t 13
Figure 2. Comparator Timing
-4-
REV. A
AD5520
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
AVCC to AVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 V AVCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V AVEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -17 V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V Digital Inputs to DGND . . . . . . . . . . -0.3 V to DVDD + 0.3 V Analog Inputs to AGND . . . . . AVCC + 0.3 V to AVEE - 0.3 V CLH to CLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +34 V CPH to CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +34 V REFGND, DGND . . . . . . . . . AVCC + 0.3 V to AVEE - 0.3 V
Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . . . 0C to 70C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature, (TJ max) . . . . . . . . . 150C Package Power Dissipation . . . . . . . . . . . . . (TJ max - TA)/ JA Thermal Impedance JA . . . . . . . . . . . . . . . . . . . . . . 47.8C/W Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300C IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD5520JST AD5520JST-REEL EVAL-AD5520EB
Temperature Range 0C to 70C 0C to 70C
Package Description 64-Lead LQFP 64-Lead LQFP Evaluation Board and Software
Package Option ST-64-2 ST-64-2
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5520 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
-5-
AD5520
PIN CONFIGURATION 64-Lead LQFP
COMPOUT2 COMPOUT1 MEASVOUT MEASIOUT MEASOUT COMPOUT0
COMPIN2
COMPIN1
COMPIN0
REFGND
REFGND
AVCC_B
50
CLH
CLL
64 CPH CPL DVDD CPOH CPOL CPCK DGND CLHDETECT CLLDETECT QM4 QM5 MOE CS STB AC0 AC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
63
62
FIN
61
60
59
58
57
56
55
54
53
52
51
49
FOH
48 47 46 45 44 43 42
AVEE_B MEASI5H MEASI4H FOH3 MEASI3H FOH2 MEASI2H FOH1 MEASI1H FOH0 MEASI0H MEASIL MEASVH GUARD(NC) MEASVL AVCC_G
AD5520
(Not to Scale)
41 40 39 38 37 36 35 34 33
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVEE_G
AVEE
STANDBY
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3, 18 4 5 6 7, 17 8 9 10 11 12 13 14 15 16
Mnemonic CPH CPL DVDD CPOH CPOL CPCK DGND CLHDETECT CLLDETECT QM4 QM5 MOE CS STB AC0 AC1
Description Upper Comparator Threshold Voltage Input, CPH > CPL. Lower Comparator Threshold Voltage Input, CPL < CPH. Digital Supply Voltage. Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH. Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL. Logic Input. Used to initiate comparator sampling and update CPOH and CPOL. Digital Ground. Logic Output. When high, indicates upper clamp active. For details, see the Clamp Function section. Logic Output. When high, indicates lower clamp active. For details, see the Clamp Function section. Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external relay or switch. For details, see the High Current Ranges section. Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external relay or switch. For details, see the High Current Ranges section. Active Low MEASOUT Enable. Active Low Logic Input. The device is selected when this pin is low. For details, see the Interface section. Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for different configurations. Rising edge of STB triggers sequence inputs. For details, see the Interface section. Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors. For details, see the Force Control Amplifier section. Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors. For details, see the Force Control Amplifier section. -6- REV. A
GUARDIN
DGND
AGND
GUARD
AM2
AM1
DVDD
AM0
AVCC
MSEL
FSEL
CPSEL
NC
AD5520
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57, 59 58 60 61 62 63 64
Mnemonic AM2 AM1 AM0 STANDBY FSEL MSEL CPSEL AVEE AVCC AGND AVEE_G GUARD NC GUARDIN AVCC_G MEASVL GUARD(NC) MEASVH MEASIL MEASI0H FOH0 MEASI1H FOH1 MEASI2H FOH2 MEASI3H FOH3 MEASI4H MEASI5H AVEE_B FOH AVCC_B COMPOUT0 COMPOUT1 COMPOUT2 COMPIN0 COMPIN1 COMPIN2 REFGND MEASOUT MEASIOUT MEASVOUT FIN CLH CLL
Description Logic Input. Used in conjunction with AM1 and AM0 to select one of six current ranges or to enable standby mode. For details, see the Current Ranges section. Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable standby mode. For details, see the Current Ranges section. Logic Input. Used in conjunction with AM2 and AM1 to select one of six current ranges or to enable standby mode. For details, see the Current Ranges section. Logic Input. When high, device is in standby mode of operation. For details, see the Standby Mode section. Logic Input. Force mode select. Used to select between current or voltage force operation. For details, see the Force Voltage or Force Current section. Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or MEASVOUT when low. Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to MEASIOUT when high. For details, see the Comparator Function and Strobing section. Most Negative Supply Voltage. Most Positive Supply Voltage. MEASx Input Ground. Most Negative Supply Voltage. Guard Output. No Connect. Guard Input. Most Positive Supply Voltage. DUT Voltage Sense Inputs (Low Sense). No Connect. DUT Voltage Sense Inputs (High Sense). DUT Current Sense Inputs (Low Sense). DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). DUT Current Sense Inputs (High Sense). Most Negative Supply Voltage. External Force Driver Control Voltage Output. Most Positive Supply Voltage. Compensation Capacitor 0 Output. Compensation Capacitor 1 Output. Compensation Capacitor 2 Output. Compensation Capacitor 0 Input. Compensation Capacitor 1 Input. Compensation Capacitor 2 Input. Analog Input/Output Reference Ground. Multiplexed DUT Voltage/Current Sense Output. For details, see the Measured Parameter section. DUT Current Sense Output. DUT Voltage Sense Output. Force Control Voltage Input. Upper Clamp Voltage Input CLH > CLL. Lower Clamp Voltage CLL < CLH.
REV. A
-7-
AD5520-Typical Performance Characteristics
0.0030 VDD = +15V VSS = -15V MODE 3 0.0030 0.0025 0.0025 VDD = +15V VSS = -15V MODE 3
VM LINEARITY (%)
0.0015
IM LINEARITY (%)
0.0020
0.0020
0.0015
0.0010
0.0010
0.0005
0.0005
0 0 10 20 30 40 TEMPERATURE ( C) 50 60 70
0 0 10 20 30 40 TEMPERATURE ( C) 50 60 70
TPC 1. Voltage Sense Amplifier Linearity vs. Temperature
TPC 4. Current Sense Linearity vs. Temperature
80 70 60 VDD = +15V VSS = -15V TA = 25 C
140 120 100
VDD = +15V VSS = -15V TA = 25 C
ISENSE CMRR
AMPLITUDE (dB)
CMRR (dB)
50 40 30 20 10 0
80 60 40 20 0
1
10
100 1k 10k FREQUENCY (Hz)
100k
1M
1
10
100 1k 10k FREQUENCY (Hz)
100k
1M
TPC 2. Voltage Sense Amplifier CMRR vs. Frequency
TPC 5. Current Sense Amplifier CMRR vs. Frequency
10 0 -10 CCOMP = 0.1nF
5 0 -5
AMPLITUDE (dB)
-20 CCOMP = 1.0nF -30 -40 CCOMP = 3.3nF -50 -60 100 VDD = +15V VSS = -15V TA = 25 C 1k 10k FREQUENCY (Hz) 100k
AMPLITUDE (dB)
-10 -15 -20 -25 -30 -35 -40 100 VDD = +15V VSS = -15V TA = 25 C 1k CCOMP = 1.0nF
CCOMP = 0.1nF
CCOMP = 3.3nF
10k FREQUENCY (Hz)
100k
TPC 3. Force Amplifier Bandwidth-MODE 0 (4 A)
TPC 6. Force Amplifier Bandwidth-MODE 1 (40 A)
-8-
REV. A
AD5520
0 -5 -10 VDD = +15V VSS = -15V TA = 25 C CCOMP = 0.1nF 0 -5 -10 VDD = +15V VSS = -15V TA = 25 C CCOMP = 0.1nF
AMPLITUDE (dB)
-20 -25 -30 -35 -40 -45 100 CCOMP = 3.3nF CCOMP = 1.0nF
AMPLITUDE (dB)
-15
-15 -20 -25 -30 -35 -40 -45 100 CCOMP = 1.0nF
CCOMP = 3.3nF
1k
10k FREQUENCY (Hz)
100k
1k
10k FREQUENCY (Hz)
100k
TPC 7. Force Amplifier Bandwidth-MODE 2 (400 A)
TPC 10. Force Amplifier Bandwidth-MODE 3 (4 mA)
5 VDD = +15V VSS = -15V TA = 25 C
30
0
20
ISENSE
AMPLITUDE (dB)
-10
AMPLITUDE (dB)
-5
10
0 VSENSE
-15
-10
-20
-20
-25
1
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
100M
-30 100
VDD = +15V VSS = -15V TA = 25 C 1k 10k 100k FREQUENCY (Hz) 1M 10M
TPC 8. Guard Amplifier Bandwidth
TPC 11. Voltage Sense and Current Sense Amplifier Bandwidths
20 10 0 VDD = +15V VSS = -15V TA = 25 C
0 VDD = +15V VSS = -15V TA = 25 C
-5
AMPLITUDE (dB)
-10 -20 -30 -40 -50 -60 100k
AMPLITUDE (dB)
-10
-15
-20
-25
1M FREQUENCY (Hz)
10M
-30 100k
1M FREQUENCY (Hz)
10M
TPC 9. Current Sense Amplifier AC PSRR
TPC 12. Force Amplifier AC PSRR-MODE 3, CCOMP = 100 pF
REV. A
-9-
AD5520
20 10 0 VDD = +15V VSS = -15V TA = 25 C 16 14 12 10 VCC
AMPLITUDE (dB)
VOLTAGE (V)
-10 -20 -30 -40 -50 -60 100k
8 6 4 2 0 -2 VDUT
1M FREQUENCY (Hz)
10M
0
5
10
15
20 25 TIME (ms)
30
35
40
45
TPC 13. Voltage Sense Amplifier AC PSRR
TPC 15. Power Up
700 600 500
VOLTAGE (V)
9 8 GUARD 7 6 5 COMPIN2 = 3000pF 4 3 2 FOH 1 COMPIN2 = 100pF COMPIN1 = 1000pF
nV/ Hz
400 300 200 100 VSENSE
0 0 10 ISENSE 100 1k FREQUENCY (Hz) 10k 100k -1 0 0.001 0.002 0.003 0.004 0.005 TIME (s) 0.006 0.007 0.008
TPC 14. Noise Spectral Density
TPC 16. Settling Time, Mode 2
-10-
REV. A
AD5520
THEORY OF OPERATION
The AD5520 is a single channel per pin parametric measurement unit (PPMU) for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and measure the corresponding current (FVMI), force current measure voltage (FIMV), force current measure current (FIMI), and force voltage measure voltage (FVMV). The PPMU can force or measure a voltage from -11 V to +11 V. It can force or measure a current over four ranges: 4 A, 40 A, 400 A, and 4 mA. The addition of an external driver allows two extended ranges. The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high. Also provided on the chip is clamp circuitry that will flag via CLHDETECT and CLLDETECT if the voltage applied to FIN or across the DUT has exceeded the voltage applied to CLL and CLH. On chip is clamp circuitry that clamps the output of the force amplifier if the voltage at MEASIOUT and MEASVOUT exceeds CLL and CLH.
INTERFACE
DAC
FIN FOHx
MEASIOUT
G = 16
MEASIHx MEASIL MEASVH MEASVL
RS
MEASVOUT
G=1
DUT
Figure 3. PMU in Standby Mode
Force Voltage or Force Current
FSEL is an input that determines whether the PPMU forces a voltage or current.
Table II. FSEL Function
FSEL Low High
Function Voltage Force and Current Clamp with MEASIOUT Voltage Current Force and Voltage Clamp with MEASVOUT Voltage
The AD5520 PPMU is controlled via a number of digital inputs, which are discussed in detail in the following sections. All inputs are TTL compatible. CS is used to select the device while STB (active low input) latches data available on the other digital inputs and updates any required digital outputs. The rising edge of STB triggers sequence inputs. The remaining digital inputs control the function of the PMU--which measure mode it is in, which compensation capacitor is used, and the selected current range.
Standby Mode
Measured Parameter
MEASOUT is a muxed output that tracks the sensed parameter, MSEL connects it to the output of either the current sense amplifier or the voltage sense amplifier, depending on which is the measured parameter of interest. The MEASOUT pin will be connected back to an ADC to allow the measured value to be converted to a digital code.
Table III. MEASOUT Connected to Voltage or Current
The AD5520 may be placed into standby mode via the standby logic input. In this mode, the force amplifier is disconnected from the force input (FIN), the switch in series with the force output pins, FOHx, is opened, and the current measure amplifier is disconnected from the sense resistors. The voltage measure amplifier is still connected across the DUT, so DUT voltage measurements may still be made while in standby mode. Figure 3 shows the configuration of the PMU while in standby mode.
Table I. Standby Mode
MSEL Low High
Function MEASOUT = DUT Voltage MEASOUT = DUT Current
The MEASOUT pin may also be made high impedance through the MOEB logic input.
Table IV. MOEB Allows MEASOUT to Go High Impedance
STANDBY Low High
Function Normal Force Mode Standby Mode
MOEB Low High
Function Enable MEASOUT Output Hi-Z MEASOUT Output
REV. A
-11-
AD5520
Current Ranges
A number of current ranges are possible with the AD5520. The AM0, AM1, and AM2 pins are digital inputs used to establish full-scale current range of the PMU.
Table V. Selection of Current Range
AM0 AM1 AM2 Function Low High Low High Low High Low High Low Low High High Low Low High High Low Current Range MODE0 (up to 4 A) Low Current Range MODE1 (up to 40 A) Low Current Range MODE2 (up to 400 A) Low Current Range MODE3 (up to 4 mA) High Current Range MODE4 (External Buffer Mode) High Current Range MODE5 (External Buffer Mode) High Standby (same as STANDBY = High) High Standby (same as STANDBY = High)
After CPSEL has selected which amplifier output is of interest, logic input CPCK is used to initiate comparator sampling and update the logic outputs CPOH and CPOL, indicating if the voltages at MEASIOUT or MEASVOUT have exceeded voltages set at CPL or CPH (thus providing DUT too high or DUT too low information). A rising edge on STB is required to clock the CPOH and CPOL data out.
Table VIII. CPCK Synchronous Logic Outputs
CPOH Low High CPOL Low High
Clamp Function
Function MEASVOUT or MEASIOUT < CPH MEASVOUT or MEASIOUT > CPH Function MEASVOUT or MEASIOUT > CPL MEASVOUT or MEASIOUT < CPL
RS Selection
The AD5520 is designed so that the voltage drop across each of the RS resistors will be less than 500 mV when maximum current is flowing through them. To support other current ranges, these sense resistor values may be changed. A force amplifier can drive a maximum of 6 mA. It is not recommended to increase the maximum current above the nominal range. The two external current ranges use an external buffer to drive the required current. Our example uses 40 mA and 160 mA ranges. These ranges can be changed to suit user requirements for a high current range.
Force Control Amplifier
Clamp circuitry is also included on chip, allowing the output of the force amplifier to be clamped in the event of the voltage at MEASIOUT and MEASVOUT exceeding CLL and CLH. The clamp circuitry play their role in the event of a short or open circuit. When in force current range, the voltage clamps protect the DUT in the event of an open circuit. Likewise, when forcing a voltage and a short circuit occurs, the current clamps will protect the DUT in this case. The clamps also function to protect the DUT in the event of a transient voltage or current spike that may occur when changing to a different operating mode or when programming the device to a different current range. The digital output flags, which indicate a clamp limit has been hit, are CLHDETECT for the upper clamp and CLLDETECT output for the lower clamp.
Table IX. Clamp Detect Outputs
The force control amplifier requires external capacitors connected between the COMPOUTx and COMPINx pins. For stability with large capacitance at the DUT, the largest capacitance value (3000 pF) should be selected. The force control amplifier should always contribute the dominant pole in the control loop. Settling times will increase with larger capacitances. ACx inputs select which external compensation capacitor is used.
Table VI. AC0, AC1 Compensation Capacitor Selection
CLHDETECT Low High CLLDETECT Low High
High Current Ranges
Function Upper Clamp Inactive Upper Clamp Active Function Lower Clamp Inactive Lower Clamp Active
AC0
AC1
Function Select External Compensation Capacitor 0 Select External Compensation Capacitor 1 Select External Compensation Capacitor 2
Low Low High Low Low High
Comparator Function and Strobing
The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high. CPSEL is the digital input that controls this function, selecting whether it should compare to the voltage sense or the current sense amplifier.
Table VII. Comparator Function Select
With the use of an external high current amplifier, two high current ranges are possible. The current range values can be selected as required in the application through appropriate selection of the sense resistors connected between MEASI5H, MEASI4H, and MEASIL. When one of these high current ranges (MODE 4 or MODE 5) is selected via the AMx control lines, the appropriate QM4 or QM5 output will be enabled. These outputs can thus be used to control relays connected in series with the high current amplifier as shown in Figure 8.
Table X. High Current Range Logic Outputs
CPSEL Low High
Function Compare CPL, CPH to MEASVOUT Compare CPL, CPH to MEASIOUT
QM4 High Low
QM5 Low High
Function Current Range MODE 4 Enable Output Current Range MODE 5 Enable Output
-12-
REV. A
AD5520
CIRCUIT OPERATION Force Voltage
Most PMU measurements are performed while in force voltage and measure current modes, for example, when the device is used as a device power supply, or in continuity or leakage testing. In the force voltage mode, the voltage at analog input FIN is mapped directly to the voltage forced at the DUT. When in force voltage and measure current modes, the maximum voltage applied to the input corresponds to the maximum current outputs. Figure 4 shows the transfer function when forcing a voltage.
VDUT
the CLL and CLH levels to ensure the clamp voltages have not been exceeded. Strobing CPCK and STB will provide information about the voltage level with respect to the comparator levels, CPH and CPL.
FIN FOHx MEASIHx VFIN G = 16 MEASIL MEASVH G=1
MEASIOUT
CLH CLL VCLH VCLL REFGNDI/V
MEASVOUT
RS
RDUT MEASVL
VCLH
RDUT RS 16
V V VCLH > IDUT VCLL < IDUT VMEASVOUT VMEASIOUT RS RS 16 16
VFIN
CONDITION OUTPUT
VCLH < IDUT VCLL < IDUT
RS RS
16 16
VCLH > IDUT VCLL > IDUT
RS RS
16 16
VCLL
RDUT RS 16
VDUT = VFIN
VDUT = VCLH
VDUT = VCLL
Figure 5. Voltage Force, Measure Current Mode
Force Current
In the force current mode, the voltage at FIN is now converted to a current through the following relationship:
IDUT
Force Current = VFIN /RSENSE
VCLH RS 16
Figure 6 shows a simplified diagram of the PMU when in force current mode. The control loop consists of the force amplifier with the current sense amplifier making up the feedback path. In this case, voltage at the DUT is sensed across the voltage measure amplifier (Gain = 1) and presented at the MEASVOUT output.
VCLH VCLL RS 16
MEASIHx VFIN G = 16 MEASIL MEASVH G=1 RDUT MEASVL RS
VCLH VFIN
FIN FOHx
CLH CLL VCLH VCLL REFGNDI/V
MEASVOUT
Measure Current
Figure 5 shows a simplified diagram of the PMU when in force voltage mode. The control loop consists of the force amplifier with the voltage sense amplifier making up the feedback path. Current flowing through the DUT is measured by sensing the current flowing through a selectable sense resistor, which is in series with the DUT. The current sense amplifier (Gain = 16) generates a voltage at its output, which is proportional to the current flowing through the DUT. This voltage is compared to
V V
VMEASVOUT VMEASIOUT VCLH > VDUT VCLL < VDUT IDUT = VFIN RS VCLH < VDUT VCLL < VDUT IDUT = VCLH RS VCLH > VDUT VCLL > VDUT IDUT = VCLL RS
CONDITION OUTPUT
Figure 6. Current Force, Voltage Measure Mode
REV. A
-13-
MEASIOUT
Figure 4. Voltage Force Transfer Function
AD5520
Figure 7 illustrates the transfer function of the current force mode.
IDUT
VCLH RDUT
external compensation capacitors are added. As mentioned, making an accurate measurement in the fastest time while avoiding overshoots and ringing is the key requirement in any ATE system. This in itself provides challenges. The external compensation capacitors set up different settling times or bandwidths on the force control amplifier, and, while one compensation capacitor value may suit one range, it may not suit other ranges. To optimize measurement performance and speed, differences in signal behavior on each range and frequency of use of each range need to be taken into account. When selecting a faster settling time, there is a trade-off between the faster settling, overshoots, and ringing. A small compensation value will result in faster settling but may incur penalties in overshoots or ringing at the DUT. Compensation capacitor selection should be optimized to ensure minimum overshoots while still giving good settling time performance. While careful selection of the compensation capacitor is required to minimize the settling time, another factor can greatly contribute to the overall settling of the loop if the feedback loop is broken in some manner and the force control amplifier goes to either the positive or negative rails. There is a finite amount of time required for the amplifier to recover from this condition, typically 85 s, which adds to the settling of the loop. Ensuring that the force control amplifier never goes into saturation is the best solution. This solution can be helped by putting the device into standby mode at any time the operating mode or range selection is changed. In addition, ensure that the selected output range can supply the required current needed by the DUT.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
VFIN
VCLL RDUT
VDUT
VCLH
VCLH VCLH VCLH VFIN
Figure 7. Current Force Transfer Function
Measure Voltage
A DUT voltage is tested via the voltage measure amplifier by a window comparator to ensure that CPH and CPL levels are not exceeded. In addition, the DUT voltage is automatically tested against the voltage levels at the clamp, and clamp flags are enabled if the DUT voltage exceeds either of the levels.
Short Circuit Protection
In any circuit where accuracy is important, careful consideration to the power supply and the ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5520 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the PMU is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. This PMU should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 F to 10 F, tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. REV. A
The AD5520 is designed to withstand a direct short circuit on any of the amplifier outputs.
SETTLING TIME CONSIDERATIONS
Fast throughput is a key requirement in automatic test equipment because it relates directly to the cost of manufacturing the DUT, thus reducing the time required to make a DAC measurement is of upmost importance. When taking measurements using a PMU, the limiting factor is usually the time it takes the output to settle to the required accuracy so a measurement can be taken. DUT capacitance, measurement accuracy, and the design of the PMU are the major contributors to this time. Figure 8 shows a simplified block diagram of the AD5520 PMU. In brief, the device consists of a force control amplifier, access to a number of selectable sense resistors, a voltage measure instrumentation amplifier, and a current measure instrumentation amplifier. To optimize the performance of the device, there are also nodes provided where
-14-
AD5520
It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance.
TYPICAL CONNECTION CIRCUIT FOR THE AD5520
Figure 8 shows the AD5520 connected as it would be in a typical application. The external components required are three compensation capacitors and six sense resistors, depending on how many ranges are required. If high current ranges > 6 mA are
required, an external amplifier must be used with relays to switch in the different current ranges to the DUT. Other components are also required to make the PMU function. The PMU requires a number of discrete voltage levels: five DAC levels for each PMU used in the system, two levels each for the comparator and clamps, and one voltage level for the AD5520 force input voltage. To utilize the information gathered from the DUT, an ADC (such as the AD7665 16-Bit ADC) must be connected to the MEASOUT pin to convert the measured current or voltage to the digital world for analysis.
3000pF 1000pF 100pF +15V -15V
COMPOUT0 COMPOUT1 COMPOUT2 COMPIN0 COMPIN1 COMPIN2
AVEE AVCC AD815 FOH FOH3 FOH2 FOH1 RELAY
AD5520
BW SELECT
FIN FORCE AMPLIFIER CLAMP DETECT CLH CLL REFGND MEASIOUT G = 16 ISENSE INST AMP MEASOUT VSENSE INST AMP G=1 G=1
FOH0 MEASI5H MEASI4H MEASI3H MEASI2H MEASI1H MEASI0H 125k MEASIL GUARDIN GUARD MEASVH MEASVL AGND < 100mV 11V DUT 12.5k 1.25k 125 12.5 < 11.5V 3.126
MEASVOUT COMPARATOR CPH CPOH
LOGICS
CLHDETECT CLLDETECT
QM5 QM4
DGND CS DVDD
CPOH
CPSEL
CPL
STB
STANDBY
MSEL
FSEL
AM2
AM1
AM0
MOE
CPCK
Figure 8. Typical Configuration of the AD5520 as Used in an ATE Circuit
REV. A
AC0 AC1
-15-
AD5520
TYPICAL APPLICATION CIRCUIT
Figure 9 shows the AD5520 as it would be used in an ATE system. This device could be used as a per pin parametric unit in order to speed up the rate at which testing could be done. It could also be used as a DUT power supply, as shown in the application circuit. The central PMU shown in the block diagram is usually a highly accurate PMU and is shared among a number of pins in the tester. In general, many discrete levels are required in an ATE system for the pin drivers, comparators, clamps, and active loads. DAC devices, such as the AD5379, offer a highly integrated solution for a number of these levels. The AD5379 is a dense 40-channel DAC designed with high channel requirements, like ATE in mind. The flexible function of the AD5520 also makes it suited for use in instrumentation applications such as source measure units. Source measure units are programmable instruments capable of sourcing and measuring voltage or current simultaneously. The AD5520 provides a more integrated solution in such equipment.
EVALUATION BOARD FOR THE AD5520 PMU
centronics connector to a PC. PC-based software to control the AD5520 is provided as part of the evaluation kit. The evaluation board schematic is shown in Figure 10. Note that VDD and VSS must provide sufficient headroom for the force and measure voltage range. In addition to the supply voltages for the evaluation board, it is also necessary to provide the following voltage levels for the clamp, comparator, and the force input pin--CLL, CLH, CPL, CPH, and FIN. SMB connections are provided for these voltage inputs. To use the evaluation board, it will also be necessary to provide a DUT connected via the gold pins. Both AGND and DGND inputs are provided on the board. The AGND and DGND planes are connected at one location close to the AD5520. It is recommended not to connect AGND and DGND elsewhere in the system to avoid ground loop problems. REFGND is routed back to AGND at the power block to maintain a clean ground reference for accurate measurements. Each supply is decoupled to the relevant ground plane with 10 F and 0.1 F capacitors. The device supply pin is again decoupled with a 10 F and 0.1 F capacitor pair to the relevant ground plane. Care should be taken when replacing devices to ensure that the pins line up correctly with the PCB pads.
A full featured evaluation kit is available for the AD5520. It consists of an evaluation board with direct hookup via a 36-way
CENTRAL PMU DAC ADC DAC DAC TIMING DATA MEMORY DAC VTERM VH RELAYS TIMING GENERATOR DLL, LOGIC FORMATTER DE-SKEW DRIVER GUARD AMP VCH
PPMU DAC ADC
DEVICE UNDER TEST (DUT) 50 COAX
DAC DAC
VL DAC
VCL GND SENSE DEVICE POWER SUPPLIES
GUARD AMP
COMPARE MEMORY
FORMATTER DE-SKEW
VTH COMP VTL
DAC ADC
DAC ACTIVE LOAD DAC IOL VCOM DAC
DAC
IOH
Figure 9. Typical Application ATE Circuit
-16-
REV. A
U2, U3, U4 BYPASS CAPACITORS
C2 10 F +5VD 18 DVDD C4 10 F 20V T7 T8 T9 T10 T11 +5VD T12 59 REFGND 57 REFGND AD815ARB R11 5k 7 9 FOH 49 4 2 R12 5k U5-A 8 3 1 8 3 +5VD 1 22 14 6 12 13 STANDBY STB CPCK MOEB CSB 27 33 50 T5 T6 AVCC AVCC_G AVCC_B J2 T4 J4 J6 J8 J3 J5 J7 J9 DVDD 3
D[0:7]
RL1
RELAY-G6H
D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 10 U3 AM0 AM1 AM2 FSEL CPSEL MSEL AC0 AC1
RELAY-G6H
D1
2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7
19 18 17 16 15 14 13 12
21 20 19 23 25 24 15 16
7
9
4
2
10
J1-1
11 C 1 OE
C Q1 E C16 10pF C R8 10k B
RL2
R6
R7
R4, 124
R1, 124k
R2, 12.4k
R3, 1.24k
Figure 10. Evaluation Board Schematic -17-
D0 D1 D2 D3 D4 D5 CPOH CPOL CHL-DET CLL-DET QM4 QM5 COMPIN2 COMPOUT2 COMPIN1 COMPOUT1 COMPIN0 COMPOUT0 8 D6 9 D7 C7, 100pF 56 53 55 52 54 51 C8, 1nF C9, 3.3nF 11 C 1 OE 2 3 4 5 6 7 4 5 8 9 10 11
R5, 12.4
REV. A
+15V C3 0.1 F Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 U2 MEASOUT MEASIOUT MEASVOUT FIN CLH CLL CPH CPL 58 60 61 62 63 64 1 2 19 18 17 16 15 14 13 12 20V C1 0.1 F D2 R9 10k MEASI5H MEASI4H FOH3 MEASI3H FOH2 MEASI2H FOH1 MEASI1H FOH0 MEASIOH MEASIL C14 47 46 45 44 43 42 41 40 39 38 37 QM5 Q1 E C15 10pF B QM4 C5 0.1 F C6 10 F 20V +5VD J10-1 C20 0.1 F J10-2 J11-1 C21 10 F 20V J11-2 C24 0.1 F J11-3 -15V 20V +15V C25 10 F 20V C22 0.1 F +15V DGND DGND 7 17 26 AVEE 29 AVEE_G 48 AVEE_B MEASVH NC MEASVL GAURDIN NC GUARD AGND 28 36 35 34 32 31 30 LK1 C17 R10 C18 C19 20V C11 0.1 F T1 U5-B 12 AD815ARB-24 U5-C -VS +VS C12 13 0.1 F C23 10 F 20V C13 10 F 16 15 T2 T3 14 AD815ARB-24 -15V C10 10 F
+5VD
74HCT573
C26 0.1 F
C27 0.1 F
C28 0.1 F
D0 D1 D2 D3 D4 D5 D6 D7
2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7
J1-14
11 C 1 OE
74HCT573
D0 D1 D2 D3 D4 D5 D6 D7
19 18 17 16 15 14 13 12
Q0 Q1 Q2 Q3
Q4 Q5 Q6 Q7
U4
74HCT573
J1-31
J1-36
J1-2 J1-3 J1-4 J1-5 J1-6 J1-7 J1-8 J1-9
D0 D1 D2 D3 D4 D5 D6 D7
J1-19 J1-20 J1-21 J1-22 J1-23 J1-24 J1-25 J1-26 J1-27 J1-28 J1-29 J1-30
AD5520
AD5520
OUTLINE DIMENSIONS
64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2)
Dimensions shown in millimeters
0.75 0.60 0.45 SEATING PLANE 12.00 BSC SQ
64 1 49 48
1.60 MAX
PIN 1
TOP VIEW
(PINS DOWN)
10.00 BSC SQ
1.45 1.40 1.35
10 6 2
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
VIEW A
16 17 32 33
0.15 0.05
SEATING PLANE
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
-18-
REV. A
AD5520 Revision History
Location 10/03--Data Sheet changed from REV. 0 to REV. A. Page
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. A
-19-
-20-
C03701-0-10/03(A)
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